The present invention relates to a method for fabricating a highly-integrated semiconductor device, and more specifically, to a method for forming a unit cell capable of making a semiconductor device operate faster and more stable.
A semiconductor memory chip includes a plurality of unit cells each of which includes a capacitor and a transistor. A double capacitor has been used to temporarily store data. A transistor transmits data between a bit line and a capacitor according to a control signal (word line). The transistor has three regions including a gate, a source and a drain, and electrical charges move between the source and the drain in response to a control signal which is applied to the gate. The electrical charges move through a channel region formed between the source and the drain.
A gate is formed on a semiconductor substrate, and impurities are doped on the substrate at both sides of the gate to form a source and a drain. To meet requirements for enhanced data capacity and integration in a semiconductor memory apparatus, unit cell size needs to be smaller. It makes the design rule applied for the capacitor and the transistor decreased. As a result, channel length becomes shorter, causing a short channel effect and a drain induced barrier lower (DIBL) effect that hinders normal operation. For preventing the short channel effect and the DIBL effect, the doping concentration of the channel region has been increased to meet a threshold voltage required in the cell transistor. However, as the design rule becomes less than 100 nm, the highly doped channel region causes electric field of a storage node (SN) junction increased, therefore deteriorating a refresh characteristic of the semiconductor memory apparatus. In order to prevent the degradation of refresh characteristic, a cell transistor with a three-dimensional structure is suggested. Such structure may secure long channel length for the cell transistor under low design rule. Moreover, if long channel length is secured, the doping concentration on the channel region can be adjusted to such a low level that would not degrade refresh characteristic. Hereinafter, a process for forming a recess-gate transistor with a three-dimensional structure is described.
FIGS. 1 to 7 are cross-sectional views illustrating a method for fabricating a general semiconductor device.
Referring to FIG. 1, a recess 104 for forming either a recess gate or a fin gate is formed on a semiconductor substrate 100 where an isolation insulating layer 102 defining an active region is formed. In this case, since either the recess gate or the fin gate is arranged in a cell array in the direction extending across the active region, the recess 104 for forming either the recess gate or the fin gate is formed in both the active region and the isolation insulating layer 102.
Thereafter, as shown in FIG. 2, a gate material is provided in the recess 104 so that a gate electrode 106 is formed.
Referring to FIG. 3, a first spacer layer 108, e.g., a nitride spacer, is deposited on the substrate and on the gate electrode 106. The first spacer nitride layer 108 is deposited to a predetermined thickness on the gate electrode 106. An oxide layer 110 is deposited on the first spacer nitride layer 108 so that a core region and a peripheral region of the semiconductor substrate 100 are covered with the oxide layer 110.
Referring to FIG. 4, after a photoresist layer (not shown) is deposited on the oxide layer 110, the photoresist layer formed on the core region is etched using a cell open mask in order to expose the core region including the cell array, so that the oxide layer 110 in the core region is exposed. Thereafter, the oxide layer 110 covering the core region is removed by a wet etching process so that a first spacer layer 108 is exposed.
Referring to FIG. 5, a second spacer layer 112, e.g., a nitride spacer, is deposited on the exposed first spacer layer 108 in the core region. The second spacer layer 112 is formed to electrically isolate the gate electrode 106 from other conductive elements like a bit line contact or a storage node contact, which will be formed between gate electrodes 106 during post processes. In order to completely isolate the contact from the gate electrodes 106, the second spacer layer 112 is generally formed with a thickness of 50˜150Å.
Referring to FIG. 6, an insulation material having superior gap-fill properties is deposited on the second spacer layer 112, and a chemical mechanical polishing (CMP) process is performed until the second spacer layer 112 is exposed. As a result, an interlayer insulating layer 114 is formed at a fine space between the gate electrodes 106.
Referring to FIG. 7, the interlayer insulating layer 114 formed in a region where a bit line contact or storage node contact in the core region will be formed is removed by an etch-back process so that a contact hole 116 is formed. The contact hole 116 is for forming a contact for connecting an active region to either a capacitor or a bit line which will be formed in a subsequent step. After the etch-back process is performed, partial portions of first and second spacer layers 108 and 112 formed at sidewalls of the gate electrode 106 still remain unetched, but the first and second spacer layers 108 and 112 formed on the active region and the isolation insulating layer 102 are completely removed. If the first and second spacer layers 108 and 112 remain on the active region, it would hinder the contact formed in the contact hole 116 from being connected to a source/drain region of a transistor. Thus, the etch-back process should be performed to a sufficient depth so as to prevent the above-mentioned problem. However, when an over etch is performed, the substrate in the active region and the isolation insulating layer 102 are attacked and damaged.
As the size of the semiconductor device shrinks gradually, an insulation material with poor gap-fill properties is not compatible with a high density plasma (HDP) deposition process to form the isolation insulating layer 102 because it results in voids within the isolation insulating layer 102. Accordingly, the isolation insulating layer 102 filling a trench (not shown) is generally composed of two insulating layers, i.e., one is with superior gap-fill properties so as to be compatible with a Spin-On-Dielectric (SOD) deposition process and the other compatible with a HDP deposition process. However, since most of insulation material subject to the HDP deposition process do not have superior gap-fill properties, it is hard to prevent the aforementioned problem.
Accordingly, a method of using insulation material that is compatible with a SOD deposition process without using insulation material compatible with a HDP deposition process for forming the isolation insulating layer 102 has been developed. However, pattern collapse or distortion is occurred because an exposed region is easily attacked due to an extremely high etch rate of the insulation material. Further, it forms a layer with irregular surface, thus causing a defect in a product. In order to overcome the above-mentioned problems, a method was recently developed for forming the isolation insulating layer 102 using both an insulation material compatible with the SOD deposition process and a Sub-Atmospheric Tetra-Ethyl Ortho Silicate (SATEOS) layer. However, some process steps for that method are so complicated and the number of process steps increases, resulting in longer Turn Around Time (TAT).
In addition, if the isolation insulating layer 102 is formed of both the insulation layer compatible with the SOD deposition process and the SATEOS layer, partial portions of the isolating layer 102 can be undesirably etched and removed by not only a first cleaning process performed after the recesses 104 are formed but also a second cleaning process performed after the interlayer insulating layer 114 and the first and second spacer layers 108 and 112 are removed. Since the recess 104 formed on the isolation insulating layer 102 can be formed wider than another recess 104 formed on the active region because of the first cleaning process, the distance between gate electrodes 106 which is formed on the isolation insulating layer 102 is reduced, resulting in a reduction of process margin. Also, due to the second cleaning process, the isolation insulating layer 102 exposed between gate electrodes 106 formed on the isolation insulating layer 102 is excessively etched so that the contact can be in electrical short with the gate electrode 106. Particularly, this electrical short causes a serious problem threatening operational stability of the semiconductor device.
FIG. 8 is a scanning electron microscope (SEM) image illustrating shortcomings of the semiconductor device manufactured by the aforementioned processes shown in FIGS. 1 to 7.
As shown, both a recess gate formed on the isolation insulating layer and a contact formed between the recess gates are electrically interconnected, so that the operational stability of the semiconductor device is deteriorated. Particularly, when a high voltage (Vpp) higher than a power-supply voltage (VDD) is supplied to each recess gate used as the word line in a semiconductor memory device while a logic low signal of a ground voltage (Vss) corresponding to data “0” are sustained in the contact, data can be unexpectedly distorted by an electrical connection between the contact and the recess gate.